1. Field of the Invention
The present invention relates generally to IC cards and, more particularly, to an IC card which stores both a test program for performing a test on the IC card itself (a product test) and an application program for performing various functions required for the use of the IC card.
2. Description of the Related Art
FIG. 6 is a block diagram showing the construction of a conventional type of IC card As illustrated, a CPU 1 is connected to both a system ROM 3 and an application ROM 4 through a bus 2.
As shown in FIG. 7, the system ROM 3 stores a test program 31 for performing a test on the IC card itself, and the application ROM 4 stores an application program 41 for performing various functions which are required for the use of the IC card. The system ROM 3 further stores a branch routine 32 first for determining whether the test program 31 or the application program 41 should be executed and then for branching to the program to be executed.
Referring back to FIG. 6, an EEPROM 5 for storing variable data, a RAM 6 for temporarily storing data, and an input/output circuit 7 for effecting data communication with external equipment are connected to the bus 2.
As shown in FIG. 8, the system ROM 3, the application ROM 4, the EEPROM 5, the RAM 6 and the input/output circuit 7 are arranged in an identical memory space. It is therefore possible to easily access a desired area of the respective memories with the same type of instruction.
Also, the system ROM 3, the application ROM 4, the EEPROM 5, the RAM 6 and the input/output circuit 7 are respectively connected to selection circuits 13, 14, 15, 16 and 17 to select the corresponding ones of these memories and the input/output circuit 7 on the basis of the arrangement of the memory space shown in FIG. 8 in accordance with the state of the bus 2.
In FIG. 6, a terminal Pl is a positive power input terminal; P2 a grounding terminal for a power source; P3 a reset signal terminal for receiving as its input a reset signal that initializes the CPU 1; P4 a clock terminal for receiving a clock signal as its input; and P5 an I/0 terminal.
Such an IC card operates in the following manner. When a reset signal is input to the IC card through the reset signal terminal P3, the CPU 1 reads out a routine starting address at which execution of the branch routine 32 is initiated, the routine starting address being stored in advance in the system ROM 3 at a predetermined address thereof. The CPU 1 initiates the execution of the branch routine 32 at this routine starting address. If an instruction for executing the test program 31 is input from external equipment (not shown) to the I/0 terminal P5 during the execution of the branch routine 32, the CPU 1 causes the process to proceed from the branch routine 32 to the ensuing test program 31. The test program 31 is provided with a function to access an arbitrary address to enable a satisfactory product test. The CPU 1 accesses individual addresses in accordance with the test program 31, thereby performing a product test.
On the other hand, if no instruction for executing the test program 31 is input, the CPU 1 reads out a program starting address at which execution of the application program 41 is initiated, the program starting address being stored in advance in the application ROM 4 at a predetermined address thereof. The CPU 1 initiates the execution of the application program 41 at this program starting address.
It is known that the above-described IC card utilizes as the CPU 1 a CPU of the type which is provided with a particular area (hereinafter referred to as a "special page") specified in the memory space and which can access the special page with an instruction word which is short compared with the lengths of instruction words used for accessing the remaining areas. The provision of such a special page contemplates an improvement in the efficiency of memory utilization. CPUs provided with the above-described special page functions are especially useful in devices such as IC cards which are required to perform a variety of functions with memories of limited capacity.
However, since such a special page in the memory space is commonly established in an area which is defined by the highest address and the adjacent high addresses as shown in FIG. 8, only a memory which is partially superimposed on the special pages defined by the highest and adjacent high addresses is capable of utilizing the special page, while the remaining memories cannot use it. More specifically, if the system ROM 3 is arranged in the area associated with the highest address as shown in FIG. 8, the special page can be used to perform the test program 31 in the system ROM 3, but the application program 41 in the application ROM 4 which is not superimposed on the special page cannot make use of the special page.